The present invention relates to a semiconductor memory device, and, more particularly, to a dynamic random access memory wherein each memory cell comprises one transistor and one capacitor, and data can be randomly read/written.
In the recent computer controlled data processing field, types and amounts of data to be processed are increasing. An important problem is indicated by the strong demand which has arisen for high speed accessing for the data read/write operation. Meanwhile, the memory capacity of a dynamic random access memory (to be referred to as a "dRAM" hereinafter) has been greatly improved in accordance with developments in the micro-patterning technique of memory cell patterns. Thus, a large amount of data can be stored in a single memory device of one chip. As a result, the demand for high speed data accessing of dRAM has increased in strength.
Today, in order to improve the data access speed of dRAM, a large number of data access drive methods have been developed and proposed. For example, a page mode dRAM has been proposed. According to a dRAM of this type, unlike a conventional memory wherein row and column address lines (i.e., word and bit lines) must be reset and pre-charged every time selection of one cell is completed, even after a cell is selected, word lines connected to the selected cell are not reset but are continuously activated. In the readout mode of this dRAM, after a desired cell is selected the word line connected thereto is left activated. Therefore, when another desired cell is designated by using only a bit line from the other cells connected to this word line, high-speed selection can be achieved. As a result, the data access speed of the page mode dRAM can be increased to twice that of a normal mode dRAM.
Furthermore, as a method of improving data access speed, a dRAM can be driven in a nibble mode. Basically, cell selection is performed so that four cells (i.e., 4 bits) connected to intersections between two adjacent word lines and two adjacent bit lines are used as one unit. During cell designation, the two word lines are continuously activated. A desired cell is designated by a shiftregister from the designated four cells. At this time, since no column address clock signal is required, the two bit lines need not be pre-charged in order to designate one desired cell from four cells. Therefore, the data access speed of the dRAM can be further improved as compared to the page mode dRAM.
According to the above dRAMs, however, the pre-charge operation cannot be completely eliminated from all the operation modes. Yet, presence of a pre-charge period means degradation in improvement in data access speed. This is because during the pre-charge period data accessing cannot be performed, with the pre-charge time undesirably protracting the time needed for data accessing. Therefore, even though the above method is used, data access speed of a dRAM is limited and cannot cope with demand for further improvement. For example, the page mode dRAM requires a pre-charge operation when data accessing is shifted from one word line to another word line, a pre-charge operation that takes the same period of time as in a normal mode dRAM. In the nibble mode dRAM, when a set (4 bits) of cells is shifted to another set (4 bits) of cells, a pre-charge operation is, likewise, required. Even in a MOS dRAM having a relatively short memory access time, e.g., 100 nano seconds, it takes 100 nano seconds to pre-charge bit lines and a clock generator.